Category: RISC-V

RVA23: From Ratification to Real-World Readiness

RVA23 was ratified in October 2024. For most of the months since, the world was essentially waiting for hardware to run it! Now the SpacemiT K3 is on shelves and more RVA23 silicon is close behind. So what was the industry up to during that time, and is the software ready for the chips that have arrived?

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Guide to Power Management on Arm & RISC-V

Guide to Power Management on Arm & RISC-V

Power management is one of the most consequential—and most misunderstood—parts of embedded Linux engineering. This white paper is a deep, practical guide to how the Linux kernel actually manages power on Arm and RISC-V platforms, written by RISCstar Principal Engineer Daniel Thompson and drawn directly from years of hands-on kernel and BSP work.

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Advancing OpenSBI Interrupt Handling

Supervisor Binary Interface, commonly known as SBI, defines how supervisor-level software – such as an operating system or a hypervisor – requests services from a more privileged execution environment. In the open-source RISC-V ecosystem, a widely used implementation of this interface is OpenSBI.

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RISC-V Summit China 2025: Reflections from a RISC-V Software Contributor (from RISC-V Blog)

The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over 4,000 attendees. The main venue was filled to capacity, with many standing along the walls just to be part of the event. This was my second time attending the RISC-V Summit, since starting development work on RISC-V, and in just two days, there was a lot to take in and reflect upon.

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