We help developers master the skills required to ship secure, high-performance products that leverage Arm and RISC-V microprocessors.
We help developers master the skills required to ship secure, high-performance products that leverage Arm and RISC-V microprocessors.
Instructor-led and hands-on training programs designed to help engineering teams port, optimize, and deploy software on modern architectures like Arm and RISC-V.
This course was developed by RISCstar for RISC-V International and the Linux Foundation
What’s Covered in This Course
This advanced and comprehensive course including hands-on labs is available online at no-charge.
RISCstar also offers this course as:
RISCstar can deliver this course both on-site and remotely for engineering teams.
With the ratification of RVA23, RISC-V processors will now include high performance vector processing capabilities in the hardware. This hands-on workshop explores RISC-V Vector (RVV) software extensions — how they work and how they dramatically accelerate compute-intensive tasks like machine learning, signal processing, and cryptography.
You’ll learn practical techniques for converting optimized C code from other ISA platforms into RVV implementations, with a focus on the key difference between fixed vector-length architectures and RVV’s flexible vector-length agnostic (VLA) approach. We’ll also go low-level, comparing Arm and RISC-V assembly to show what’s truly possible on the metal.
Sharpen your skills and get hands-on enabling high performance software with vector computing.
Originally developed for RISC-V International this hands-on workshop compares AI operator vectorization between Arm SVE and RVV 1.0 at the ISA level.
Using tools like perf and disassembly, you’ll analyze intrinsic patterns, memory access behavior, and execution efficiency — exploring key architectural differences including tail policy vs. predication and vector length control.
You’ll leave with practical optimization strategies for RVV-based AI kernels and real-world insights into migrating from SVE to RVV.
Ideal for engineers and researchers building AI software on RISC-V platforms.
This three-day Rust introductory course is specifically designed for engineers with embedded experience and includes hands-on labs. What’s covered in this course
★ Rust basics
★ Rust <> C
★ Rust for embedded
★ Rust for Linux
Devicetree, drivers, upstreaming, profiling, real-time constraints
Trusted Firmware-A, OP-TEE TEEs, secure manufacturing & OTA
Unlock the full potential of hardware with software
Board bring-up, drivers, connectivity stacks, secure boot
BSPs, build reproducibility, CI automation
Hypervisor fundamentals, scheduler and CPU utilization tuning
Tailor modules to your SoC, board, and product constraints.
Practical learning using debuggers, trace tools, virtualization, and power instrumentation.
Optional post-course engagement to help apply knowledge to shipping features.
Reference materials, sample code, workflow guides for long-term value.
Your engineers are the foundation of your success, RISCstar helps them reach their full potential.
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