Fast forward to 2025, and the tone has shifted. This year, the pressure is on. The question is no longer whether RISC-V can attract interest—it’s when it will truly deliver.
Nowadays, it is (rightfully) impossible to put an embedded device into the market without comprehensive embedded device security measures. Most new devices store private data that we do not want to see leaked in dark corners of the Internet. We also want to avoid our device ending up as part of a botnet.
The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over 4,000 attendees. The main venue was filled to capacity, with many standing along the walls just to be part of the event. This was my second time attending the RISC-V Summit, since starting development work on RISC-V, and in just two days, there was a lot to take in and reflect upon.
Idle states allow parts of the CPU to be de-clocked and/or powered off to minimize the power they consume. These features, selectively disabling clock or power to parts of the circuit, are sometimes referred to as clock- or power-gating.
Learn how Linux kernel technical debt impacts embedded systems. Discover causes, costs, warning signs, and proven strategies to manage kernel debt effectively.
New hardware designs must go through an initial “bring-up” process to ensure it functions as intended
Today, RISC-V is starting to look less like a fringe alternative and more like a strategic necessity—especially in China.
Today’s new hardware is impressive, but it’s easy to overlook the critical role software plays in maximizing hardware performance
This talk highlights the importance of upstreaming support for RISC-V to the Linux kernel, urging vendors from China’s RISC-V industry and academia to take a more active role in contributing support for RISC-V to the open-source ecosystem
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