Introducing the RISCstar toolchain for RISC-V
October 22, 2025
Daniel Thompson, tech lead for the RISCstar toolchain, shares a few of the technical details behind this new toolchain for RISC-V.
Daniel Thompson, tech lead for the RISCstar toolchain, shares a few of the technical details behind this new toolchain for RISC-V.
The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over 4,000 attendees. The main venue was filled to capacity, with many standing along the walls just to be part of the event. This was my second time attending the RISC-V Summit, since starting development work on RISC-V, and in just two days, there was a lot to take in and reflect upon.
Idle states allow parts of the CPU to be de-clocked and/or powered off to minimize the power they consume. These features, selectively disabling clock or power to parts of the circuit, are sometimes referred to as clock- or power-gating.
Copyright © 2025 RISCstar Solutions Corporation. All Rights Reserved